Rapid Assured Access (R2A)

Statement of Objectives 26-6F4 Rapid Assured Access (R2A) 1.0 Introduction The mission of the Defense Microelectronics Activity (DMEA) is to deliver microelectronics solutions to meet the needs of the Department of War (DoW). DMEA ensures the rapid acquisition and insertion of technology by focusing on the Warfighter’s needs by researching current and emerging microelectronics issues, leveraging advanced technologies to extend the life of weapon systems, improving reliability, maintainability, and performance, and addressing the problem of diminishing manufacturing sources. An important part of this effort is DMEA’s role in ensuring the DoW has access to a reliable and secure supply chain of manufacturers of semiconductor foundry technologies. DMEA oversees the Trusted Access Program Office (TAPO), whose purpose is to facilitate USG access to microelectronics production, aggregate demand, and oversee the production of critical microelectronics components. TAPO is entrusted with developing and maintaining a reliable source of suppliers that give DoW programs and defense contractors access to advanced processes and services. The purpose of this Rapid Response Assessment program is to establish a rapid and reliable source for domestically produced custom-designed microelectronics for the Department of Defense (DoD). This initiative aims to mitigate critical supply chain risks by leveraging the capabilities of the U.S. commercial semiconductor industry. 2.0 Scope The scope of Rapid Assured Access (R2A) program is to provide rapid, long-term assured semiconductor foundry access, regardless of project size and classification, through enterprise-wide contracts executed by TAPO for DoW programs and defense contractors. TAPO will establish a R2A contract vehicle that provides rapid access to microelectronics manufacturers and an on ramp of additional vendors, through that vehicle, as required to mitigate future technology gaps. The goal of R2A is to establish multiple single-award IDIQ’s to meet the government’s technology needs and secondly, meet the assurance need to DoW as they develop. 3.0 Program Objective The primary objective is for the awardees to provide foundry access to Defense contractors (the Defense Industrial Base (DIB)) and program offices via this contract vehicle. The intent is for the awardees to leverage this vehicle to rapidly provide TAPO clients with a quick-turn contract vehicle that has pre-negotiated terms and conditions. Negotiating a long-term contract with TAPO once saves the Government and the awardee time and effort by avoiding repeated negotiations over terms and conditions for each procurement. Forward wafer and other pricing shall be provided for clients who require use of the vehicle and can be refreshed at pre-determined junctures (1-2 years typically). The intent of R2A is to work directly with the wafer manufacturing foundry. A wafer manufacturing foundry is a production qualified wafer fab that consists of Front End of Line (FEOL) and Back End of Line (BEOL) manufacturing steps commonly referred to as lithography, diffusion, chemical vapor deposition, etch, and other associated processes. DMEA/TAPO will not be the primary user of this vehicle but rather a service provider that administers the contract vehicle. 4.0 Operating Environment and Constraints Any proposed solution must operate within the following constraints: 4.1. Commercial Business Model: The Government seeks to adopt commercial acquisition practices. Solutions should be structured around a Firm-Fixed-Price (FFP) model, including separate charges for Non-Recurring Engineering (NRE) and per-wafer production costs. 5.0 Requirements The primary objective is for the awardees to provide foundry access to Defense contractors (the Defense Industrial Base (DIB)) and program offices via this contract vehicle. 5.1 Process Technologies Required The contractor shall provide (internally manufacture via its owned and operated semiconductor foundry), production-qualified, domestic (US), semiconductor foundry technologies for the USG. (e.g., lithographic -- 1 of 4 -- generations: 32-nm bulk CMOS, 180-nm SiGe, 1 micron Bi-CMOS, SOI, 7-nm Fin-FET, Silicon Photonics technologies, Group III-V compound semiconductor technologies fabrication, or others). A semiconductor foundry is defined as a production qualified wafer fab that consists of Front End of Line (FEOL) and Back End of Line (BEOL) manufacturing steps commonly referred to as lithography, diffusion, chemical vapor deposition, etch, and other associated processes.) Capabilities shall be tooled to industry-standard silicon wafer sizes (150mm, 200mm, 300mm). 5.1.1. U.S. Domestic Operations: All fabrication and handling of Government, designs and hardware must occur within the continental United States. 5.1.2. For any technologies offered, the offeror shall have ISO9001:2015 certification. 5.1.3. Photomask Sourcing: The ability to produce or otherwise obtain masks that are production qualified for the proposed technologies. Domestically manufactured masks are highly preferred. 5.1.4. The commercial operating temperature (0-70 degrees Celsius) is required, Industrial or Automotive is preferred. Military/Aerospace is highly preferred. 5.2 Base Intellectual Property For the Technologies offered, the contractor shall provide foundational base intellectual property (IP), such as standard cell libraries. For compound semiconductor technologies, standard logic cells and component library, power integration, RF and Microwave, I/O, and protection and control blocks are preferred. Reference designs such as Low Noise Amplifiers (LNAs) and Power Amplifiers are highly preferred. 5.3 Process Design Kit Support For the Technologies referenced in section 5.1, the contractor shall provide process design kits (PDKs) that include schematic symbols, layout cells, and automated design rule checks (DRC) for Electronic Design Automation (EDA) tools such as, but not limited to, Caden…